This invention relates generally to electrostatic discharge (ESD) circuits and, more particularly, to an ESD protection circuit and method for use with integrated circuits having input pads without significantly increasing the parasitic capacitance at the input pads.
Integrated circuits (IC) normally require ESD protection. ESD protection is conventionally provided at bond pads and/or input/output pads of the IC. In this manner ESD protection is provided to internal circuitry of the IC, such as transistors etc., from ESD spike voltages that exceed the rating of the active devices of the IC. Typically, electrostatic discharge voltage spikes occur at the input pads during handling of the IC.
The prior art is replete with myriad of ESD integrated protection circuits. Typical ESD protection circuits divert ESD generated voltages occurring at input pads to the power rails of the IC circuits employing such protection. The input pads, for example, are clamped to approximately VDD or VSS (the operating voltages applied to the IC) by using ESD protection diodes depending on the polarity of the ESD voltages. Thus, for instance, in response to an ESD voltage established at an input pad of a first polarity (positive) exceeding the forward breakdown voltage of one of the ESD protection diode, current flow is oriented from the pad via the ESD protection diode to the high potential power rail (VDD). Likewise, if the ESD voltage established at the input pad is of a second polarity and exceeds the forward breakdown voltage of the second ESD protection diode, current flow is oriented from ground (VSS) via the second ESD protection diode to the pad. Hence, both positive and negative ESD occurrences are clamped to the power rails by the aforementioned action of the ESDP diodes. Similarly, the output pads are also protected from ESD spike voltages by a like pair of diodes.
Most, if not all, conventional ESD protection circuits typically produce significantly large input capacitance at the input/output pads of the integrated circuit. The increased capacitance is due to the relatively large conductive elements such as the metal pads or conductive patterns associated with the integrated circuit as well as resistors, and the base-emitter junctions of the ESDP diodes of the protection circuit. In some applications, this increased capacitance at the input pads of the integrated ESD protection circuit cannot be tolerated. For example, the integrated circuit employing a conventional ESD protection may be used to probe the output of a pressure sensor. Typically, such pressure sensors provide a small delta output voltage. In order to detect the output of the sensor, the capacitance at the input of the probing device must be as small of value as possible.
Hence, a need exists to provide an integrated ESD protection circuit in which the capacitance thereof is reduced to a minimum value.
In accordance with an aspect of the present invention, there is provided an electrostatic discharge (ESD) protection circuit for protecting circuitry internal to an integrated circuit from ESD damage due to ESD voltage that may occur at the input of the integrated circuit while minimizing any effective input capacitance appearing at the input. The ESD protection circuit includes at least one pair of opposite conductivity type diodes coupled between the input and an internal circuit node which provide current paths between the input and the power rails of the integrated when forward bias by ESD voltages. A unity gain amplifier provides feedback to maintain a zero voltage difference between the input and the internal circuit node thereby reducing the effective capacitance to substantially zero.